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CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Features

Watchdog timer Clock alarm with programmable interrupts Capacitor or battery backup for RTC Commercial and industrial temperatures 44 and 54-pin TSOP II package Pb-free and RoHS compliance
20 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14B104K) or 256K x 16 (CY14B104M) Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrap nonvolatile elements is initiated by software, device pin, or AutoStore on power down RECALL to SRAM is initiated by software or power up High reliability Infinite Read, Write, and RECALL cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 3V +20%, -10% operation Data integrity of Cypress nvSRAM combined with full featured Real Time Clock (RTC)
Functional Description
The Cypress CY14B104K and CY14B104M combines a 4 Mbit nonvolatile static RAM with a full featured RTC in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM is read and written infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. The RTC function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for periodic minutes, hours, days, or months alarms. There is also a programmable watchdog timer for process control.
Quatrum Trap 2048 X 2048 VCC V CA
P
Logic Block Diagram[1, 2, 3]
A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A 18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I N P U T B U F F E R S R O W D E C O D E R STATIC RAM ARRAY 2048 X 2048
STORE RECALL
POWER CONTROL
VRTCbat VRTCcap
STORE/RECALL CONTROL SOFTWARE DETECT
HSB
A14 - A2
RTC
Xout Xin INT
COLUMN I/O MUX A18- A 0 OE WE
COLUMN DEC
CE A9 A10 A11 A 12 A13 A14 A15 A 16 BLE
BHE
Notes 1. Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration. 2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. 3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation Document #: 001-07103 Rev. *M
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 15, 2009
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Pinouts
Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II
INT [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 Xout Xin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC [4] NC A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 VRTCcap VRTCbat
INT [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB [4] NC
A17 A16
A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC
44 - TSOP II
(x8)
54 - TSOP II
(x16)
Top View (not to scale)
Top View (not to scale)
Xout Xin
VRTCcap VRTCbat
Table 1. Pin Definitions Pin Name A0 - A18 A0 - A17 DQ0 - DQ7
DQ0 - DQ15
I/O Type Input
Description Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select One of the 262,144 words of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation. Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on operation. No Connect No Connects. This pin is not connected to the die. Input Input Input Input Input Output Input Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Crystal Connection. Drives crystal on startup. Crystal Connection. For 32.768 KHz crystal.
NC WE CE OE BHE BLE Xout Xin VRTCcap VRTCbat
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used. Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
Notes 4. Address expansion for 8 Mbit. NC pin not connected to die. 5. Address expansion for 16 Mbit. NC pin not connected to die.
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Table 1. Pin Definitions (continued) Pin Name INT VSS VCC HSB I/O Type Output Ground Description Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). Ground for the Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs to the Device. 3.0V +20%, -10% Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is driven HIGH for short time with standard output high current. Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.
VCAP
Device Operation
The CY14B104K/CY14B104M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14B104K/CY14B104M supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the Truth Table For SRAM Operations on page 24 for a complete description of read and write modes.
AutoStore Operation
The CY14B104K/CY14B104M stores data to the nvSRAM using one of three storage operations. These three operations are: Hardware STORE, activated by the HSB; Software STORE, activated by an address sequence; AutoStore, on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104K/CY14B104M. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 5. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This may corrupt the data stored in nvSRAM. Figure 2. AutoStore Mode
Vcc
SRAM Read
The CY14B104K/CY14B104M performs a read cycle whenever CE and OE are LOW, and WE and HSB are HIGH. The address specified on pins A0-18 or A0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. Byte Enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF 10kOhm Vcc
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DO0-15 are written into the memory if it is valid tSD before the end of a WE controlled write or before the end of a CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
WE VCAP
V SS
VCAP
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Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 15 for the size of the VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull up should be placed on WE to hold it inactive during power up. This pull up is only effective if the WE signal is tristate during power up. Many MPUs tristate their controls on power up. Verify this when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore, and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B104K/CY14B104M Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Hardware STORE (HSB) Operation
The CY14B104K/CY14B104M provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B104K/CY14B104M conditionally initiates a STORE operation after tDELAY. An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B104K/CY14B104M. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B104KA/CY14B104MA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B104K/CY14B104M remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on powerup, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited.
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Table 2. Mode Selection CE H L L L WE X H L H OE, BHE, BLE[3] X L X L A15 - A0[6] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Standby Active Active Active[7]
L
H
L
Active[7]
L
H
L
Active ICC2[7]
L
H
L
Active[7]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Notes 6. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are don't care. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
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Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.
The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
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Data Protection
The CY14B104K/CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B104K/CY14B104M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.
Setting the Clock
Setting the write bit `W' (in the flags register at 0x7FFF0) to a `1' stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time is then written into the registers and must be in 24 hour BCD format. The time written is referred to as the "Base Time". This value is stored in nonvolatile registers and used in the calculation of the current time. Resetting the write bit to `0' transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation. If the time written to the timekeeping registers is not in the correct BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation. Note The values entered in the timekeeping, alarm, calibration, and interrupt registers need a STORE operation to be saved in nonvolatile memory. Therefore, while working in AutoStore disabled mode, the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly.
Noise Considerations
Refer to CY application note AN1064.
Real Time Clock Operation
nvTIME Operation
The CY14B104K/CY14B104M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format. RTC functionality is described with respect to CY14B104K in the following sections. The same description applies to CY14B104M, except for the RTC register addresses. The RTC register addresses for CY14B104K range from 0x7FFF0 to 0x7FFFF, while those for CY14B104M range from 0x3FFF0 to 0x3FFFF. Refer to Table 4 on page 11 and Table 5 on page 12 for a detailed Register Map description.
Backup Power
The RTC in the CY14B104K is intended for permanently powered operation. The VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH the device switches to the backup power supply. The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost. During backup operation, the CY14B104K consumes a maximum of 300 nanoamps at room temperature. User must choose capacitor or battery values according to the application. Backup time values based on maximum current specifications are shown in the following table. Nominal backup times are approximately two times longer. Table 3. RTC Backup Time Capacitor Value 0.1F 0.47F 1.0F Backup Time 72 hours 14 days 30 days
Clock Operations
The clock registers maintain time up to 9,999 years in one second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as `0' are currently not used and are reserved for future use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. The user must stop internal updates to the CY14B104K time keeping registers before reading clock data, to prevent reading of data in transition. Stopping the register updates does not affect clock accuracy. The updating process is stopped by writing a `1' to the read bit `R' (in the flags register at 0x7FFF0), and does not restart until a `0' is written to the read bit. The RTC registers are then read while the internal clock continues to run. After a `0' is written to the read bit (`R'), all RTC registers are simultaneously updated within 20 ms.
Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3V lithium is recommended and the CY14B104K sources current only from the battery when the primary power is removed. However the battery is not recharged at any time by the CY14B104K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the "enabled" (set to 0) state. To preserve the battery life when the system is in storage, OSCEN Page 7 of 33
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must be set to `1'. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. While system power is off, If the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail.The CY14B104K has the ability to detect oscillator failure when system power is restored. This is recorded in the OSCF (Oscillator Failed bit) of the flags register at the address 0x7FFF0. When the device is powered on (VCC goes above VSWITCH) the OSCEN bit is checked for "enabled" status. If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set to "1". The system must check for this condition and then write `0' to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the "Base Time" (see Setting the Clock on page 7), which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the `oscillator failed' condition. The value of OSCF must be reset to `0' when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit "W" (in the Flags register at 0x7FFF0) to a "1" to enable writes to the Flag register. Write a "0" to the OSCF bit and then reset the write bit to "0" to disable writes.
toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of -10 (001010b) must be loaded into the Calibration register to offset this error. Note Setting or changing the Calibration register does not affect the test output frequency. To set or clear CAL, set the write bit "W" (in the flags register at 0x7FFF0) to "1" to enable writes to the Flag register. Write a value to CAL, and then reset the write bit to "0" to disable writes.
Alarm
The alarm function compares user programmed values of alarm time and date (stored in the registers 0x7FFF1-5) with the corresponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on INT pin if Alarm Interrupt Enable (AIE) bit is set. There are four alarm match fields - date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to `0' indicates that the corresponding field is used in the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. Selecting all match bits (all 0s) causes an exact time and date match. There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at 0x7FFF0 indicates that a date or time match has occurred. The AF bit is set to "1" when a match occurs. Reading the flags register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event. To set, clear or enable an alarm, set the `W' bit (in Flags Register - 0x7FFF0) to `1' to enable writes to Alarm Registers. After writing the alarm value, clear the `W' bit back to "0" for the changes to take effect. Note CY14B104K requires the alarm match bit for seconds (0x7FFF2 - D7) to be set to `0' for proper operation of Alarm Flag and Interrupt.
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystals available in market typically have an error of +20 ppm to +35 ppm. However, CY14B104K employs a calibration circuit that improves the accuracy to +1/-2 ppm at 25C. This implies an error of +2.5 seconds to -5 seconds per month. The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in Calibration register at 0x7FFF8. The calibration bits occupy the five lower order bits in the Calibration register. These bits are set to represent any value between `0' and 31 in binary form. Bit D5 is a sign bit, where a `1' indicates positive calibration and a `0' indicates negative calibration. Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary `1' is loaded into the register, it corresponds to an adjustment of 4.068 or -2.034 ppm offset in oscillator error, depending on the sign. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once every minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary `1' is loaded into the register, only the first two minutes of the 64-minute cycle are modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.068 or -2.034 ppm of adjustment per calibration step in the Calibration register. To determine the required calibration, the CAL bit in the Flags register (0x7FFF0) must be set to `1'. This causes the INT pin to
Watchdog Timer
The Watchdog Timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the Watchdog Timer register. The timer consists of a loadable register and a free running counter. On power up, the watchdog time out value in register 0x7FFF7 is loaded into the Counter Load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe (WDS) bit is set to `1'. The counter is compared to the terminal value of `0'. If the counter reaches this value, it causes an internal flag and an optional interrupt output. You can prevent the time out interrupt by setting WDS bit to `1' prior to the counter reaching `0'. This causes the counter to reload with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and WDT flag never occur.
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New time out values are written by setting the watchdog write bit to `0'. When the WDW is `0', new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When WDW is `1', writes to bits D5-D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 3. Note that setting the watchdog time out value to `0' disables the watchdog function. The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out. If the Watchdog Interrupt Enable (WIE) bit in the Interrupt register is set, a hardware interrupt on INT pin is also generated on watchdog timeout. The flag and the hardware interrupt are both cleared when user reads the Flags registers. Figure 3. Watchdog Timer Block Diagram
Oscillator
32,768 KHz
determine the cause of the interrupt. The INT pin driver has two bits that specify its behavior when an interrupt occurs. An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled (set to `1'). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the Flags register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section. Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. Note CY14B104K generates valid interrupts only after the Powerup Recall sequence is completed. All events on INT pin must be ignored for tHRECALL duration after powerup.
Clock Divider
32 Hz
1 Hz
Counter
Zero Compare
WDF
Interrupt Register
Watchdog Interrupt Enable - WIE. When set to `1', the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs. When WIE is set to `0', the watchdog timer only affects the WDF flag in Flags register. Alarm Interrupt Enable - AIE. When set to `1', the alarm match drives the INT pin and an internal flag. When AIE is set to `0', the alarm match only affects the AF Flags register. Power Fail Interrupt Enable - PFE. When set to `1', the power fail monitor drives the pin and an internal flag. When PFE is set to `0', the power fail monitor only affects the PF flag in Flags register. High/Low - H/L. When set to a `1', the INT pin is active HIGH and the driver mode is push pull. The INT pin drives high only when VCC is greater than VSWITCH. When set to a `0', the INT pin is active LOW and the drive mode is open drain. The INT pin must be pulled up to Vcc by a 10k resistor while using the interrupt in active LOW mode. Pulse/Level - P/L. When set to a `1' and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to a `0', the INT pin is driven high or low (determined by H/L) until the Flags or Control register is read. When an enabled interrupt source activates the INT pin, an external host reads the Flags registers to determine the cause. Remember that all flags are cleared when the register is read. If the INT pin is programmed for Level mode, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for Pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete its specified duration if the Flags register is read. If the INT pin is used as a host reset, the Flags register is not read during a reset.
WDS
Load Register
D Q
WDW
Q
write to Watchdog Register
.
Watchdog Register
Power Monitor
The CY14B104K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access. The power monitor is based on an internal band gap reference circuit that compares the VCC voltage to VSWITCH threshold. As described in the section AutoStore Operation on page 3, when VSWITCH is reached as VCC decays from power loss, a data STORE operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from VCC to the backup supply (battery or capacitor) to operate the RTC oscillator. When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not available to the user. The clock continues to operate in the background. The updated clock data is available to the user tHRECALL delay after VCC is restored to the device (see AutoStore/Power Up RECALL on page 21).
Interrupts
The CY14B104K has Flags register, Interrupt register, and Interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x7FFF6). In addition, each has an associated flag bit in the Flags register (0x7FFF0) that the host processor uses to
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. They are set by the watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts when a flag is set. These flags are automatically reset after the register is read. The flags register is automatically loaded with the value 0x00 on power up (except for the OSCF bit. See Stopping and Starting the Oscillator on page 7). Page 9 of 33
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Figure 4. RTC Recommended Component Configuration
Recommended Values Y1 = 32.768 KHz (12.5 pF) C1 = 12 pF C2 = 69 pF
Note: The recommended values for C1 and C2 include board trace capacitance.
C1 C2
Y1
Xout Xin
Figure 5. Interrupt Block Diagram
WDF Watchdog Timer WIE PF Power Monitor VINT H/L AF Clock Alarm AIE PFE P/L Pin Driver
VCC
INT
VSS
WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low
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Table 4. RTC Register Map[8] Register CY14B104K CY14B104M 0x7FFFF 0x7FFFE 0x7FFFD 0x7FFFC 0x7FFFB 0x7FFFA 0x7FFF9 0x7FFF8 0x7FFF7 0x7FFF6 0x7FFF5 0x7FFF4 0x7FFF3 0x7FFF2 0x7FFF1 0x7FFF0 0x3FFFF 0x3FFFE 0x3FFFD 0x3FFFC 0x3FFFB 0x3FFFA 0x3FFF9 0x3FFF8 0x3FFF7 0x3FFF6 0x3FFF5 0x3FFF4 0x3FFF3 0x3FFF2 0x3FFF1 0x3FFF0 WDF 0 0 0 0 0 0 OSCEN (0) WDS (0) WIE (0) M (1) M (1) M (1) M (1) 0 WDW (0) AIE (0) 0 0 PFE (0) 0 D7 D6 0 0 0 0 10s Years 0 10s Months 0 0 BCD Format Data[9] D5 D4 D3 D2 Years Months Day Of Month Day of Week Hours Minutes Seconds Calibration (00000) WDT (000000) H/L (1) P/L (0) 0 0 D1 D0 Function/Range Years: 00-99 Months: 01-12 Day of Month: 01-31 Day of Week: 01-07 Hours: 00-23 Minutes: 00-59 Seconds: 00-59 Calibration Values [10] Watchdog [10] Interrupts [10] Alarm, Day of Month: 01-31 Alarm, Hours: 00-23 Alarm, Minutes: 00-59 Alarm, Seconds: 00-59 Centuries: 00-99 R (0) Flags[10]
10s Day of Month 0 10s Minutes 10s Seconds Cal Sign (0) 10s Hours
10s Alarm Date 10s Alarm Hours 10 Alarm Minutes 10 Alarm Seconds
Alarm Day Alarm Hours Alarm Minutes Alarm, Seconds Centuries
10s Centuries AF PF OSCF 0
CAL (0)
W (0)
Notes 8. Upper byte D15-D8 (CY14B104MA) of RTC registers are reserved for future use. 9. ( ) designates values shipped from the factory. 10. This is a binary value, not a BCD value.
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Table 5. Register Map Detail Register CY14B104K 0x7FFFF CY14B104M 0x3FFFF D7 D6 D5 10s Years Description Time Keeping - Years D4 D3 D2 Years D1 D0
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Time Keeping - Months 0x7FFFE 0x3FFFE D7 0 D6 0 D5 0 D4 10s Month D3 D2 Months D1 D0
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. 0x7FFFD 0x3FFFD Time Keeping - Date D7 0 D6 0 D5 D4 D3 D2 D1 D0 10s Day of Month Day of Month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1-31. Leap years are automatically adjusted for. 0x7FFFC 0x3FFFC Time Keeping - Day D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 Day of Week D0
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date. 0x7FFFB 0x3FFFB Time Keeping - Hours D7 0 D6 0 D5 D4 D3 D2 Hours D1 D0 10s Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. 0x7FFFA 0x3FFFA Time Keeping - Minutes D7 0 D6 D5 10s Minutes D4 D3 D2 D1 Minutes D0
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. 0x7FFF9 0x3FFF9 Time Keeping - Seconds D7 0 D6 D5 10s Seconds D4 D3 D2 D1 Seconds D0
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0-59.
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Table 5. Register Map Detail (continued) Register CY14B104K 0x7FFF8 CY14B104M 0x3FFF8 D7 OSCEN OSCEN Calibration Sign Calibration 0x7FFF7 0x3FFF7 D6 0 D5 Calibration Sign Description Calibration/Control D4 D3 D2 Calibration D1 D0
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. These five bits control the calibration of the clock. WatchDog Timer D7 WDS D6 WDW D5 D4 D3 WDT D2 D1 D0
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5-D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to 0 allows bits D5-D0 to be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in Watchdog Timer on page 8. Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle. Interrupt Status/Control 0x3FFF6 D7 WIE D6 AIE D5 PFE D4 0 D3 H/L D2 P/L D1 0 D0 0
WDW
WDT
0x7FFF6
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag. Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm match only affects the AF flag. Power Fail Enable. When set to 1, the power fail monitor drives the INT pin and the PF flag. When set to 0, the power fail monitor affects only the PF flag. Reserved for future use High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW. Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read. 0x3FFF5 Alarm - Day D7 M D6 0 D5 D4 D3 D2 D1 D0 10s Alarm Date Alarm Date
AIE PFE 0 H/L P/L
0x7FFF5
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. M Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value.
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Table 5. Register Map Detail (continued) Register CY14B104K 0x7FFF4 CY14B104M 0x3FFF4 D7 M M D6 D5 10s Alarm Hours Description Alarm - Hours D4 D3 D2 D1 D0 Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value. Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. 0x3FFF3 Alarm - Minutes D7 M M D6 D5 10s Alarm Minutes D4 D3 D2 D1 D0 Alarm Minutes
0x7FFF3
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the minutes value. 0x3FFF2 Alarm - Seconds D7 M M D6 D5 10s Alarm Seconds D4 D3 D2 D1 D0 Alarm Seconds
0x7FFF2
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds' value. Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value. 0x3FFF1 Time Keeping - Centuries D7 D6 D5 D4 D3 D2 D1 Centuries D0 10s Centuries
0x7FFF1
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries. 0x7FFF0 0x3FFF0 Flags D7 WDF WDF AF PF OSCF D6 AF D5 PF D4 OSCF D3 0 D2 CAL D1 W D0 R
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power up. Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared to 0 when the Flags register is read or on power up. Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid. This bit survives power cycle and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up. Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping counters if the time has changed (a new base time is loaded). This bit defaults to 0 on power up. Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.
CAL W
R
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Maximum Accumulated Storage Time At 150C Ambient Temperature................................... 1000h At 85C Ambient Temperature..................... ........... 20 Years Ambient Temperature with Power Applied ............................................ -55C to +150C Supply Voltage on VCC Relative to GND ..........-0.5V to 4.1V Voltage Applied to Outputs in High Z State ....................................... -0.5V to VCC + 0.5V Input Voltage.......................................... -0.5V to VCC + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260C DC Output Current (1 output at a time, 1s duration).....15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) Parameter Description Test Conditions Power Supply VCC Average VCC Current tRC = 20 ns ICC1 tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) ICC2 ICC3 ICC4 ISB IIX[12] Average VCC Current during STORE Average VCC Current at tRC = 200 ns, VCC (Typ), 25C Average VCAP Current during AutoStore Cycle VCC Standby Current Min 2.7 Commercial Typ[11] 3.0 Max 3.6 65 65 50 70 70 52 10 35 Unit V mA mA mA mA mA mA
Industrial
All Inputs Don't Care, VCC = Max. Average current for duration tSTORE All I/P cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). All Inputs Don't Care, VCC = Max. Average current for duration tSTORE
5
mA
IOZ VIH VIL VOH VOL VCAP
CE > (VCC - 0.2V). VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. Input Leakage Current VCC = Max, VSS < VIN < VCC -1 (except HSB) Input Leakage Current VCC = Max, VSS < VIN < VCC -100 (for HSB) Off State Output VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or -1 Leakage Current BHE/BLE > VIH or WE < VIL Input HIGH Voltage 2.0 Input LOW Voltage VSS - 0.5 Output HIGH Voltage IOUT = -2 mA 2.4 Output LOW Voltage IOUT = 4 mA Storage Capacitor Between VCAP pin and VSS, 5V Rated 61
5
mA A A A V V V V F
+1 +1 +1 VCC + 0.5 0.8 0.4 180
68
Notes 11. Typical values are at 25C, VCC= VCC (Typ). Not 100% tested. 12. The HSB pin has IOUT = -2 uA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested.
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Data Retention and Endurance
Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 20 200 Unit Years K
Capacitance
In the following table, the capacitance parameters are listed. [13] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC (Typ) Max 7 7 Unit pF pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[13] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 6. AC Test Loads 44 TSOP II 31.11 5.56 54 TSOP II 30.73 6.08 Unit C/W C/W
JA JC
577 3.0V OUTPUT 30 pF R2 789 R1
577 3.0V OUTPUT 5 pF R2 789 R1
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <3 ns Input and Output Timing Reference Levels .................... 1.5V
Note 13. These parameters are only guaranteed by design and are not tested.
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RTC Characteristics
Parameters VRTCbat IBAK[14] Description RTC Battery Pin Voltage RTC Backup Current TA (Min) 25C TA (Max) VRTCcap
[15]
Min 1.8
Typ[11] 3.0 350
Max 3.3 350 500
Units V nA nA nA V V V sec
RTC Capacitor Pin Voltage
TA (Min) 25C TA (Max)
1.6 1.5 1.4 450
3.0 3.0 3.0 1
3.6 3.6 3.6 2 850
tOCS RBKCHG
RTC Oscillator Time to Start RTC Backup Capacitor Charge Current-Limiting Resistor
Notes 14. From either VRTCcap or VRTCbat. 15. If VRTCcap > 0.3V or if no capacitor is connected to VRTCcap pin, the oscillator starts in tOCS time. If a backup capacitor is connected and vrtccap < 0.3V, the capacitor must be allowed to charge to 0.3V for oscillator to start.
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AC Switching Characteristics
Parameters Cypress Alt Parameters Parameters SRAM Read Cycle tACE tACS [16] tRC tRC tAA tAA [17] tDOE tOE [17] tOH tOHA tLZCE [13, 18] tLZ tHZCE [13, 18] tHZ [13, 18] tLZOE tOLZ tHZOE [13, 18] tOHZ tPU [13] tPA [13] tPD tPS tDBE tLZBE[13] [13] tHZBE SRAM Write Cycle tWC tWC tWP tPWE tSCE tCW tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR [13, 18,19] tHZWE tWZ tLZWE [13, 18] tOW tBW 20 ns Description Min Max 25 ns Min Max 45 ns Min Max Unit
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write
20 20 20 10 3 3 8 0 8 0 20 10 0 8 20 15 15 8 0 15 0 0 8 3 15 3 20 25 20 20 10 0 20 0 0 0 0 0 3 3 25
25 45 25 12 3 3 10 0 10 0 25 12 0 10 45 30 30 15 0 30 0 0 10 3 30
45 45 20
15 15 45 20 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled[16, 17, 20]
tRC Address Address Valid tAA Data Output Previous Data Valid tOHA Output Data Valid
Notes 16. WE must be HIGH during SRAM read cycles. 17. Device is continuously selected with CE, OE and BHE / BLE LOW. 18. Measured 200 mV from steady state output voltage. 19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 20. HSB must remain HIGH during Read and Write cycles.
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Figure 8. SRAM Read Cycle 2: CE Controlled[3, 16, 20]
Address Address Valid tACE tAA tLZCE OE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance tPU Standby Active Output Data Valid tPD tDOE tHZBE tHZOE tRC tHZCE
CE
ICC
Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21]
tWC Address Address Valid tSCE CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input tHZWE Data Output Previous Data tHD Input Data Valid tLZWE High Impedance tHA
Note 21. CE or WE must be >VIH during address transitions.
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Switching Waveforms
Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21]
tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA
Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22] (Not applicable for RTC register writes)
tWC Address tSCE CE tSA BHE, BLE tAW tPWE WE tSD Data Input Data Output tHD Input Data Valid High Impedance tBW tHA Address Valid
Note 22. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
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AutoStore/Power Up RECALL
Parameters tHRECALL [23] tSTORE [24] tDELAY [25] VSWITCH tVCCRISE[13] VHDIS[13] tLZHSB[13] tHHHD[13] Description Power Up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Write Cycle Low Voltage Trigger Level VCC Rise Time HSB Output Disable Voltage HSB To Output Active Time HSB High Active Time 20 ns Min Max 20 8 20 2.65 1.9 5 500 Min 25 ns Max 20 8 25 2.65 1.9 5 500 Min 45 ns Max 20 8 25 2.65 1.9 5 500 Unit ms ms ns V s V s ns
150
150
150
Switching Waveforms
Figure 12. AutoStore or Power Up RECALL[26]
VCC VSWITCH VHDIS
VVCCRISE tHHHD HSB OUT tLZHSB
Note
24
tSTORE tHHHD tDELAY tLZHSB
Note
24
tSTORE Note
27
AutoStore POWERUP RECALL Read & Write Inhibited (RWI)
tDELAY
tHRECALL
tHRECALL
POWER-UP RECALL
Read & Write
BROWN OUT AutoStore
POWER-UP RECALL
Read & Write
POWER DOWN AutoStore
Notes 23. tHRECALL starts from the time VCC rises above VSWITCH. 24. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 25. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 27. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.
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Software Controlled STORE and RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed. [28, 29] Parameters tRC tSA tCW tHA tRECALL tSS [33, 34] Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 20 ns Min Max 20 0 15 0 200 100 25 ns Min Max 25 0 20 0 200 100 45 ns Min Max 45 0 30 0 200 100 Unit ns ns ns ns s s
Switching Waveforms
Figure 13. CE and OE Controlled Software STORE and RECALL Cycle[29]
tRC Address tSA CE tSA OE tHHHD HSB (STORE only) DQ (DATA) tLZCE tHZCE t DELAY Note
32
tRC Address #6 tCW tHA tHA
Address #1 tCW
tHA
tHA
High Impedance tSTORE/tRECALL
tLZHSB
RWI
Figure 14. Autostore Enable and Disable Cycle
tRC Address tSA CE tSA OE tLZCE DQ (DATA) tHZCE tSS Note
32
tRC Address #6 tCW
Address #1 tCW tHA tHA
tHA
tHA
t DELAY
Notes 28. The software sequence is clocked with CE controlled or OE controlled reads. 29. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles. 30. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 31. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 32. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
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CY14B104K, CY14B104M
Hardware STORE Cycle
Parameters tDHSB tPHSB Description HSB To Output Active Time when write latch not set Hardware STORE Pulse Width 15 20 ns Min Max 20 15 Min 25 ns Max 25 15 Min 45 ns Max 25 Unit ns ns
Switching Waveforms
Figure 15. Hardware STORE Cycle[24]
Write latch set
tPHSB HSB (IN) tDELAY HSB (OUT) DQ (Data Out) RWI tLZHSB tSTORE tHHHD
Write latch not set
tPHSB HSB (IN) HSB pin is driven high to VCC only by Internal 100kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. tDELAY tDHSB tDHSB
HSB (OUT) RWI
Figure 16. Soft Sequence Processing[33, 34]
Soft Sequence Command Address Address #1 tSA Address #6 tCW
tSS
Soft Sequence Command Address #1 Address #6 tCW
tSS
CE VCC
Notes 33. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 34. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
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CY14B104K, CY14B104M
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE H L L L WE X H H L OE X L H X Inputs and Outputs[2] High Z Data Out (DQ0-DQ7); High Z Data in (DQ0-DQ7); Read Output Disabled Write Mode Deselect/Power Down Active Active Active Power Standby
For x16 Configuration
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE[3] X H L H L L H L L H L BLE[3] X H L L H L L H L L H Inputs and Outputs[2] High Z High Z Data Out (DQ0-DQ15) Data Out (DQ0-DQ7); DQ8-DQ15 in High Z Data Out (DQ8-DQ15); DQ0-DQ7 in High Z High Z High Z High Z Data In (DQ0-DQ15) Data In (DQ0-DQ7); DQ8-DQ15 in High Z Data In (DQ8-DQ15); DQ0-DQ7 in High Z Mode Deselect/Power down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Active Active Active Active Active Active Active Active Active Active Power Standby
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C T
Option: T - Tape & Reel Blank - Std. Pb-Free P - 54 Pin Blank - 44 Pin Package: ZS - TSOP II Data Bus: K - x8 + RTC M - x16 + RTC
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns
Density: 104 - 4 Mb
Voltage: B - 3.0V NVSRAM 14 - AutoStore + Software STORE + Hardware STORE
Cypress
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Ordering Information
Speed (ns) 20 Ordering Code CY14B104K-ZS20XCT CY14B104K-ZS20XC CY14B104K-ZS20XIT CY14B104K-ZS20XI CY14B104M-ZSP20XCT CY14B104M-ZSP20XC CY14B104M-ZSP20XIT CY14B104M-ZSP20XI 25 CY14B104K-ZS25XCT CY14B104K-ZS25XC CY14B104K-ZS25XIT CY14B104K-ZS25XI CY14B104M-ZSP25XCT CY14B104M-ZSP25XC CY14B104M-ZSP25XIT CY14B104M-ZSP25XI 45 CY14B104K-ZS45XCT CY14B104K-ZS45XC CY14B104K-ZS45XIT CY14B104K-ZS45XI CY14B104M-ZSP45XCT CY14B104M-ZSP45XC CY14B104M-ZSP45XIT CY14B104M-ZSP45XI
All the above parts are Pb-free.
Package Diagram 51-85087 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85187 51-85160 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85187 51-85160 51-85160 51-85160 51-85160
Package Type 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII
Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Package Diagrams
Figure 17. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087 *A
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CY14B104K, CY14B104M
Package Diagrams
(continued) Figure 18. 54-Pin TSOP II (51-85160)
51-85160 **
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Document History Page
Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 431039 TUP See ECN New Data Sheet *A 489096 TUP See ECN Removed 48 SSOP Package Added 44 TSOPII and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform Added RTC Characteristics Table Added RTC Recommended Component Configuration *B 499597 PCI See ECN Removed 35ns speed bin Added 55ns speed bin. Updated AC table for the same Changed "Unlimited" read/write to "infinite" read/write Features section: Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles. Shaded Commercial grade in operating range table. Modified Icc/Isb specs. Changed VCAP value in DC table Added 44 TSOP II in Thermal Resistance table Modified part nomenclature table. Changes reflected in the ordering information table. *C 517793 TUP See ECN Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35F Changed VIH max to VCC + 0.5V Changed tSTORE to 15ns Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min. specification for Vswitch Changed tGLAX to 1ns Added tDELAY max. of 70us Changed tSS specification from 70us min. to 70us max. *D 825240 UHA See ECN Changed the data sheet from Advance information to Preliminary Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW in 15ns part to 15ns *E 914280 UHA See ECN Changed the figure-14 title from 54-Pb to 54 Pin Included all the information for 45ns part in this data sheet
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No. Description of Change Change Date *F 1890926 vsutmp8/AESee ECN Added Footnote 1, 2 and 3. SA Updated Logic Block diagram Updated Pin definition Table Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8) package. Corrected typo in VIL min spec Changed the value of ICC3 from 25mA to 13mA Changed ISB value from 1mA to 2mA Updated ordering information table Rearranging of Footnotes. Changed Package diagrams title. The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout diagram. *G 2267286 GVCH/PYRS See ECN Rearranging of "Features" Added BHE and BLE Information in Pin Definitions Table Updated Figure 2 (Autostore mode) Updated footnote 6 RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0 Register Map Detail:0x1FFF6:Changed D4 from ABE to 0 and removed ABE information Changed ICC2 & ICC4 from 3mA to 6mA Changed ICC3 from 13mA to 15mA Changed ISB from 2mA to 3mA Added input leakage current (IIX) for HSB in DC Electrical Characteristics table Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Corrected typo in tDBE value from 22ns to 20ns for 45ns part Corrected typo in tHZBE value from 22ns to 15ns for 45ns part Corrected typo in tAW value from 15ns to 10ns for 15ns part Changed Vrtccap max from 2.7V to 3.6V Changed tRECALL from 100 to 200us Added footnote 10, 29 Reframed footnote 18, 25 Added footnote 18 to figure 8 (SRAM WRITE Cycle #1) Added footnote 18, 26 and 27 to figure 9 (SRAM WRITE Cycle #2) *H 2483627 GVCH/PYRS See ECN Removed 8 mA typical ICC at 200 ns cycle time in Feature section Referenced footnote 9 to ICC3 in DC Characteristics table Changed ICC3 from 15 mA to 35 mA Changed Vcap minimum value from 54 uF to 61 uF Changed tAVAV to tRC Changed VRTCcap minimum value from 1.2V to 1.5V Figure 12:Changed tSA to tAS and tSCE to tCW *I 2519319 GVCH/PYRS 06/20/08 Added 20 ns access speed in "Features" Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade Updated Thermal resistance values for 44-TSOP II and 54-TSOP II packages Added AC Switching Characteristics specs for 20 ns access speed Added Software controlled STORE/RECALL cycle specs for 20 ns access speed Updated ordering information and Part numbering nomenclature
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No. Description of Change Change Date *J 2600941 GVCH/PYRS 11/04/08 Removed 15 ns access speed from "Features" Changed part number from CY14B104K/CY14B104M to CY14B104KA/CY14B104MA Updated Logic block diagram Updated footnote 1 Added footnote 2 Pin definition: Updated WE, HSB and NC pin description Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description Page 4: Updated Hardware store operation and Hardware RECALL (Power up) description Footnote 1 and 8 referenced for Mode selection Table Updated footnote 6 Page 6: updated Data protection description Page 6: Updated Starting and stopping the oscillator description Page 7: Updated Calibrating the clock description Page 7: Updated Alarm description Page 8: Added Flags register Added footnote 10 and 11 Updated Figure 4: Removed RF register and Changed C2 value from 56pF to 12pF Updated Register Map Table 3 Updated Register map detail Table 4 Maximum Ratings: Added Max. Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed ICC2 from 6mA to 10mA Changed ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Updated ICC1, ICC3, ISB and IOZ Test conditions Changed VCAP voltage max value from 82uF to 180uF Updated footnote 12 and 13 Added footnote 14 Added Data retention and Endurance Table Updated Input Rise and Fall time in AC test Conditions Changed tOCS value for minimum temperature from 10 to 2 sec updated tOCS value for room temperature from 5 to 1sec Referenced footnote 20 to tOHA parameter Updated All switching waveforms Updated footnote 20 Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled) Updated tDELAY value Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 27 Added footnote 29 Software controlled STORE/RECALL Table: Changed tAS to tSA Changed tGHAX to tHA Changed tHA value from 1ns to 1ns Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added truth table for SRAM operations Updated ordering information and part numbering nomenclature
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Document Number: 001-07103 Orig. of Submission Rev. ECN No. Description of Change Change Date *K 2653928 GVCH/PYRS 02/04/09 Changed Part number from CY14B104KA/CY14B104MA to CY14B104K/CY14B104M Updated Real Time Clock operation description Added factory default values to register map table 3 Added footnote 9 Updated Flag register description in Table 4 Updated C1, C2 values to 21pF, 21pF respectively Changed IBAK value from 350 nA to 450 nA at hot temperature Changed VRTCcap typical value from 2.4V to 3.0V Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZBE, tLZWE, tHZWEand tHZBE Added footnote 22 Updated Figure 13 *L 2710240 GVCH/PYRS 05/22/09 Moved data sheet status from Preliminary to Final Changed pin names X1, X2 to Xout, Xin respectively. Updated AutoStore operation Updated C1, C2 values to 12pF, 69pF from 21pF, 21pF respectively Updated ISB test condition Updated footnote 11 Updated IBAK and VRTCcap parameter values Added RBKCHG parameter to RTC characteristics table Added footnote 15 Referenced footnote 13 to VCCRISE, tHHHD and tLZHSB parameters Updated VHDIS parameter description *M 2738586 GVCH 07/15/09 Page 4: Updated Hardware STORE (HSB) operation description page 4: Updated Software STORE description Added best practices Updated tDELAY parameter description Updated footnote 25 and added footnote 32 Referenced footnote 32 to Figure 13 and Figure 14
Document #: 001-07103 Rev. *M
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CY14B104K, CY14B104M
Sales, Solutions, and Legal Information
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(c) Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07103 Rev. *M
Revised July 15, 2009
Page 33 of 33
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